The present invention relates to an EEPROM or a flash EEPROM or the like, and in particular, a nonvolatile semiconductor memory device in which data is programmed before data erasure.
In general, a non-volatile semiconductor memory device such as an EPROM and a flash EEPROM has memory cells each of which comprises a transistor having a stacked gate structure in which a control gate is stacked on a floating gate. In order to program data in a flash EEPROM of, e.g., an NOR type memory cell array, a voltage for programming is applied across a control gate and a drain to generate channel hot electrons, and the hot electrons are injected into the floating gate.
In order to erase the data programmed in the memory cell, a high voltage is applied across the control gate and source, whereby electrons captured by the floating gate are discharged therefrom to the source due to a tunnel phenomenon.
The above data erasure has a problem of over-erase which causes that the threshold voltage of the memory cell becomes negative. To be more specific, if data its excessively erased from a memory cell (which is hereinafter referred to as an over-erase cell), the cell is in the ON-state even when it is not selected. Thus, if a memory cell which stores data "0" and is in the OFF state is connected to a bit line connected to an over-erase cell, even when the "0" data stored memory cell is selected, a correct data cannot be read out via the bit line.
In order to prevent the above over-erase in the flash memory, data erasure and a verify operation for the data erasure are repeatedly carried out, and the data erasure is ended when the threshold voltage of the one of the memory cells which requires the longest time period for data erasure lowers to a predetermined voltage. Such operations are executed by an automatic erasure control section provided in the semiconductor memory chip.
However, in the flash EEPROM, the variation of the threshold voltages of the memory cells is 2V or more and considerably great, as compared with data erasure using ultraviolet rays, in which the variation of the threshold voltages of the memory cells falls within the range of 1V or less. Thus, the lower limit of the program voltage is restricted.
In view of the above, in order to reduce the variation of the threshold voltages after data erasure, the following pre-program operation (a program operation prior to data erasure) is performed: data is programmed in all the memory cells of the memory cell array of the flash EEPROM before application of an erase voltage, whereby electrons are injected into the floating gates of all the memory cells. The preprogram operation is controlled by the automatic data erasure control section provided in the semiconductor memory chip. To be more specific, in the pre-program operation, data is fixed at "0", and then is programmed in memory cells in units of one memory cell block, while changing the addresses of the memory cell blocks.
Conventionally, the following two methods have been proposed as the pre-program operations:
In the first method, the program operation is performed regardless of the data stored the memory cells in the memory cell array. To be more specific, as shown in FIG. 7, data "0" is programmed in all the memory cells, while incrementing the addresses of the memory cells. In this method, the program operation is performed for a time period in which the threshold voltages of the memory cells will be sufficiently increased, while without verifying the threshold voltages of the memory cells. Thus, in the pre-program operation according to the first method, there is a possibility that electrons may excessively be injected into the floating gates of the memory cells.
In the second method, the data stored in the memory cells of the memory cell array is checked, and the program operation is performed only on a memory cell the threshold voltage of which is low. In this case, before the program operation, the threshold voltages of the memory cells, as shown in FIG. 8, are verified (ST71, ST72), and data is programmed only in the memory cell the threshold voltage of which is low (ST73, ST74). Thereafter, data programming is verified, and if it is verified that the data programming is insufficient, the program operation is re-performed. This operation is performed on all the memory cells, while incrementing the addresses of the memory cells. Therefore, according to the second method, the threshold voltages of all the memory cells can be set at the same value.
If spare row lines to be used for defective row lines are provided in the memory cell array, the preprogram operation is performed on the memory cell of the defective row lines and the memory cells of the spare row lines, in order to prevent over-erase from occurring in those memory cells.
However, if a defective memory cell is present, in which the floating gate and the control gate short-circuit, the defective memory cell does not enter the OFF state; it is always in the ON state, even after the program operation is performed. Thus, when a sequential operation, as shown in FIG. 8, including a verify operation is performed on the defective memory cell, it is not finished since the threshold voltage of the defective memory cell is not increased. Therefore, the pre-program operation performed on the defective memory cell must not be verified.
In a conventional flash EEPROM, the pre-program operation and the verify operation, both shown in FIG. 8, are performed as illustrated in FIGS. 9A, 9B, 10A, 10B, and 11. Specifically, in units of one row line, the data of memory cells is successively verified, and data is programmed in the memory cells. If an address of a defective row line is hit, the data of memory cells connected to a spare row line replaced by the defective row line is verified, and data is programmed in the memory cells of the spare row line. To be more specific, as shown in FIG. 9A, row lines in a memory cell array 94 are successively selected in accordance with the operation of an address counter 91, an address buffer 92 and a row address decoder 93, and data of memory cells connected to the selected row lines is verified (steps ST101 and ST102 in FIG. 11). Based on the verification result, data "0" is set and programmed in those of the memory cells of the selected row line, the threshold voltages of which are low (steps ST104 to ST107 in FIG. 11).
If a defective row line is designated, a replacing signal RDHIT outputted from a defective row address storing section 95 including fuses (not shown) rises to a high level "H". As a result, a spare row decoder 96, instead of a row decoder 93, selects a spare row line 97. In this state, the data of memory cells connected to the spare row line 97 is verified, and then data is programmed in the memory cells. Here, the row decoder 93 receives a replacement prohibiting signal RDDIS having a low level "L".
In this case, the defective row line is not selected, and thus neither the verify operation nor the program operation is performed on the memory cells of the defective row line. If the memory cell array 94 include no defective row line, the spare row line 97 is not selected. In other words, the spare row line 97 is not used (See FIG. 9B).
After completing programming processing of the memory cells connected to the last one of the row lines in the memory cell array 94, the program operation is performed on memory cells of the defective row line and memory cells connected to the spare row line. When the memory cell array 94 includes a defective row line, the address of the defective row line, as shown in FIG. 10A, is read out from the defective row address storing section 95, and is supplied to an address buffers 92 (ST108). At the same time, a spare use signal SPE outputted from the defective row address storing section 95 is set at a high level, and the replacement prohibiting signal RDDIS is set at a high level, thereby selecting the defective row line. In this state, the program operation is performed on the memory cells of the defective row line, without performing the verify operation (ST109 to ST112).
On the other hand, when no defective row line is included in the memory cell array 94, the spare use signal SPE outputted from the defective row address storing section 95 is set at a low level. Thus, as shown in FIG. 10B, a unused spare row line is forcibly selected (ST109, ST113). In this state, data is programmed in memory cells connected to the selected spare row line without performing the verify operation (ST111, ST112).
However, the above pre-program operation includes a sequential operation specific for the defective row line, and as a result, an automatic data erasing circuit is complicated. Furthermore, it is necessary to read out the address of the defective row line from the defective row address storing section 95, and feed back the defective row address to the address buffer 92. Thus, the circuit structure is also complicated.
Specifically, the defective row address storing section 95, as shown in FIG. 12, needs to have a defective row address storing element 95a comprising, e.g., fuses (not shown) for storing the address of a defective row line, a coincidence detecting circuit 95b for comparing an input row address with the address of the defective row line, a buffer circuit 95e connected to an output terminal of the coincidence detecting circuit 95b, for outputting a coincidence signal RDHIT, a buffer circuit 95c connected to the defective row address storing element 95a, for outputting a spare use signal SPE, and a buffer circuit 95d connected to the defective row address storing element 95a, for reading out the address of the defective row line, and feeding back the address to the address buffer. In such a manner, the circuit structure and the layout of structural element are complicated.